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1 fn9124.11 isl6840, isl6841, isl6842, isl6843, isl6844, isl6845 improved industry standard single-ended current mode pwm controller the isl6840, isl6841, isl6842, isl6843, isl6844, isl6845 family of adjustable frequency, low power, pulse width modulating (pwm) current mode controllers is designed for a wide range of power conversion applications including boost, flyback, and isolated output configurations. peak current mode control effectively handles power transients and provides inherent overcurrent protection. this advanced bicmos design is pin compatible with the industry standard 384x family of controllers and offers significantly improved perfor mance. features include low operating current, 60a start-up current, adjustable operating frequency to 2mhz, and high peak current drive capability with 20ns rise and fall times. pinouts isl6840, isl6841, isl6842, isl6843, isl6844, isl6845 (8 ld soic, msop) top view isl6840, isl6841, isl6842, isl6843, isl6844, isl6845 (8 ld dfn) top view features ? 1a mosfet gate driver ? 60a start-up current, 100a maximum ? 25ns propagation delay current sense to output ? fast transient response with peak current mode control ? adjustable switching frequency to 2mhz ? 20ns rise and fall times with 1nf output load ? trimmed timing capacitor di scharge current for accurate deadtime/maximum duty cycle control ? high bandwidth error amplifier ? tight tolerance voltage reference over line, load, and temperature ? tight tolerance current limit threshold ? pb-free available (rohs compliant) applications ? telecom and datacom power ? wireless base station power ? file server power ? industrial power systems ? pc power supplies ? isolated buck and flyback regulators ? boost regulators part number rising uvlo (v) max. duty cycle (%) isl6840 7.0 100 isl6841 7.0 50 isl6842 14.4 100 isl6843 8.4 100 isl6844 14.4 50 isl6845 8.4 50 comp fb rtct vref vdd out gnd 1 2 3 4 8 cs 7 6 5 2 3 4 1 7 6 5 8 comp fb cs rtct vref vdd out gnd data sheet february 23, 2012 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americ as inc. 2004, 2005, 2007, 2008, 2012. all rights reserved intersil (and design) is a trademark owned by in tersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
2 fn9124.11 february 23, 2012 ordering information part number (note 4) part marking temp range (c) package pkg. dwg. # isl6840ibz (notes 1, 3) 6840 ibz -40 to +105 8 ld soic (pb-free) m8.15 isl6840irz-t (notes 2, 3) 40z -40 to +105 8 ld 2x3 dfn (pb-free) l8.2x3 isl6840iuz (notes 1, 3) 6840z -40 to +105 8 ld msop (pb-free) m8.118 isl6841ib-t isl 6841ib -40 to +105 8 ld soic m8.15 isl6841ibz (notes 1, 3) 6841 ibz -40 to +105 8 ld soic (pb-free) m8.15 isl6841irz-t (notes 2, 3) 41z -40 to +105 8 ld 2x3 dfn (pb-free) l8.2x3 isl6841iuz (notes 1, 3) 6841z -40 to +105 8 ld msop (pb-free) m8.118 isl6842ibz (notes 1, 3) 6842 ibz -40 to +105 8 ld soic (pb-free) m8.15 isl6842irz-t (notes 2, 3) 42z -40 to +105 8 ld 2x3 dfn (pb-free) l8.2x3 isl6842iuz (notes 1, 3) 6842z -40 to +105 8 ld msop (pb-free) m8.118 isl6843cbz (notes 1, 3) 6843 cbz 0 to +70 8 ld soic (pb-free) m8.15 isl6843ibz (notes 1, 3) 6843 ibz -40 to +105 8 ld soic (pb-free) m8.15 isl6843irz-t (notes 2, 3) 43z -40 to +105 8 ld 2x3 dfn (pb-free) l8.2x3 isl6843iu-t 6843 -40 to +105 8 ld msop m8.118 isl6843iuz (notes 1, 3) 6843z -40 to +105 8 ld msop (pb-free) m8.118 isl6844ibz (notes 1, 3) 6844 ibz -40 to +105 8 ld soic (pb-free) m8.15 isl6844irz-t (notes 2, 3) 44z -40 to +105 8 ld 2x3 dfn (pb-free) l8.2x3 isl6844iuz (notes 1, 3) 6844z -40 to +105 8 ld msop (pb-free) m8.118 isl6845ibz (notes 1, 3) 6845 ibz -40 to +105 8 ld soic (pb-free) m8.15 ISL6845IRZ-t (notes 2, 3) 45z -40 to +105 8 ld 2x3 dfn (pb-free) l8.2x3 isl6845iuz (notes 1, 3) 6845z -40 to +105 8 ld msop (pb-free) m8.118 isl6841eval3z evaluation board isl6844eval1z evaluation board isl6844eval2z evaluation board isl6844eval3z evaluation board notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. contact factory for availability. 3. these intersil pb-free plastic packaged pr oducts employ special pb-free material sets , molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 4. for moisture sensitivity level (msl), please see device information page for isl6840 , isl6841 , isl6842 , isl6843 , isl6844 , isl6845 .for more information on msl please see tech brief tb363 . isl6840, isl6841, isl6842, isl6843, isl6844, isl6845
3 fn9124.11 february 23, 2012 functional block diagram on vdd cs fb rtct gnd pwm comparator reset dominant 2.5v enable 8.4ma 2.6v 0.7v oscillator comparator + - uvlo comparator v ref 5.00v + - bg + - 100mv error amplifier + - vref + - on + - s r q q comp vref uv comparator 4.65v 4.80v bg + - a = 0.5 + - clock 1.1v clamp 2r r t q q isl6841/isl6844/isl6845 p/n uvlo on/off -40, -41 7.0/6.6v -42, -44 14.3/8.8v -43, -45 8.4/7.2v a vref fault v dd ok vref out only isl6840, isl6841, isl6842, isl6843, isl6844, isl6845
4 fn9124.11 february 23, 2012 typical application - 48v input dual output flyback vin+ vin- return t1 q3 36v to 75v vr1 +1.8v +3.3v c1 c2 c3 r1 r3 c4 q1 r4 cr6 c5 r22 u2 cr2 cr5 cr4 c17 r21 u3 r16 c14 c13 r15 r19 r17 r18 r20 c15 c16 c12 c11 r13 c8 r10 r6 cr1 + + c21 c19 c22 c20 + + c6 isl684x v dd rtct cs fb out comp vref gnd r26 r27 u4 isl6840, isl6841, isl6842, isl6843, isl6844, isl6845
5 fn9124.11 february 23, 2012 typical application - boost converter vin+ vin- c1 q1 r1 r4 cr1 c9 c8 r7 c2 c5 c6 c7 r3 + r2 c4 l1 c3 vin+ u1 isl684x out cs rtct fb comp vref vdd gnd +vout return r5 r6 r8 c10 isl6840, isl6841, isl6842, isl6843, isl6844, isl6845
6 fn9124.11 february 23, 2012 absolute maximum rati ngs thermal information supply voltage, v dd . . . . . . . . . . . . . . . . . . . gnd - 0.3v to +20.0v out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to v dd + 0.3v signal pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to 6.0v peak gate current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1a operating conditions temperature range isl684xix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +105c isl684xcx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0c to +70c supply voltage range (typical, note 8) isl6840, isl6841. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5v to 14v isl6843, isl6845. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9v to 16v isl6842, isl6844. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15v to 18v thermal resistance (typical) ja (c/w) jc (c/w) dfn package (notes 5, 6) . . . . . . . . . . 77 6 soic package (note 5) . . . . . . . . . . . . 100 n/a msop package (notes 5, 7) . . . . . . . . 165 62 maximum junction temperature . . . . . . . . . . . . . . .-55c to +150c maximum storage temperature range . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 5. ja is measured with the component mounted on a high effective t hermal conductivity test board in free air. see tech brief tb379 for details. 6. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 7. for jc , the ?case temp? location is taken at the package top center. 8. all voltages are with respect to gnd. electrical specifications recommended operating conditions unless otherwise noted. refer to ?functional block diagram? and ?typical application? schematic on pages 3 and 4. v dd = 15v (note 12), r t = 10k , c t = 3.3nf, t a = -40c to +105c (industrial) or t a = 0c to +70c (commercial) , typical values are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +105c or 0c to +70c . parameter test conditions min (note 9) typ max (note 9) units undervoltage lockout start threshold (isl6840, isl6841) 6.5 7.0 7.5 v start threshold (isl6843, isl6845) 7.8 8.4 9.0 v start threshold (isl6842, isl6844) 13.3 14.3 15.3 v stop threshold (isl6840, isl6841) 6.1 6.6 6.9 v stop threshold (isl6843, isl6845) 6.7 7.2 7.7 v stop threshold (isl6843c only) 6.6 7.2 7.8 v stop threshold (isl6842, isl6844) 8.0 8.8 9.6 v hysteresis (isl6840, isl6841) -0.4 - v hysteresis (isl6843, isl6845) -0.8 - v hysteresis (isl6842, isl6844) -5.4 - v start-up current, i dd v dd < start threshold - 60 100 a operating current, i dd (note 10) - 3.3 4.0 ma operating supply current, i d includes 1nf gate loading - 4.1 5.5 ma reference voltage overall accuracy over line (v dd = 12v to 18v), load, temperature 4.925 5.000 5.050 v overall accuracy (isl6843c only) 4.82 5.000 5.18 v long term stability t a = +125c, 1000 hours (note 11) - 5 - mv fault voltage 4.40 4.65 4.85 v vref good voltage 4.60 4.80 vref - 0.05 v hysteresis 50 165 250 mv isl6840, isl6841, isl6842, isl6843, isl6844, isl6845
7 fn9124.11 february 23, 2012 current limit, sourcing -20 --ma current limit, sinking 5 --ma current sense input bias current v cs = 1v -1.0 - 1.0 a cs offset voltage v cs = 0v (note 11) 95 100 105 mv comp to pwm comparator offset voltage v cs = 0v (note 11) 0.80 1.15 1.30 v input signal, maximum 0.91 0.97 1.03 v input signal, maximum (isl6843c only) 0.9 0.97 1.07 v gain, a cs = v comp / v cs 0 < v cs < 910mv, v fb = 0v (note 11) 2.5 3.0 3.5 v/v cs to out delay (note 11) - 25 40 ns cs to out delay (isl6843c only) (note 11) 70 ns error amplifier open loop voltage gain (note 11) 60 90 - db open loop voltage gain (isl6843c only) (note 11) 55 db unity gain bandwidth (note 11) 3.5 5-mhz reference voltage v fb = v comp 2.475 2.514 2.55 v fb input bias current v fb = 0v -1.0 -0.2 1.0 a comp sink current v comp = 1.5v, v fb = 2.7v 1.0 --ma comp source current v comp = 1.5v, v fb = 2.3v -0.4 --ma comp voh v fb = 2.3v 4.80 - vref v comp vol v fb = 2.7v 0.4 - 1.0 v psrr frequency = 120hz, v dd = 12v to 18v (note 11) 60 80 - db oscillator frequency accuracy initial, t j = +25c 49 52 55 khz frequency variation with v dd t = +25c (f 18v - f 12v )/f 12v -0.2 1.0 % temperature stability (note 11) - - 5 % amplitude, peak-to-peak -1.9 - v rtct discharge voltage -0.7 - v discharge current rtct = 2.0v 7.2 8.4 9.5 ma output gate voh v dd to out, i out = -200ma - 1.0 2.0 v gate vol out to gnd, i out = 200ma - 1.0 2.0 v peak output current c out = 1nf (note 11) - 1.0 - a rise time c out = 1nf (note 11) - 20 40 ns fall time c out = 1nf (note 11) - 20 40 ns pwm electrical specifications recommended operating conditions unless otherwise noted. refer to ?functional block diagram? and ?typical application? schematic on pages 3 and 4. v dd = 15v (note 12), r t = 10k , c t = 3.3nf, t a = -40c to +105c (industrial) or t a = 0c to +70c (commercial) , typical values are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +105c or 0c to +70c . (continued) parameter test conditions min (note 9) typ max (note 9) units isl6840, isl6841, isl6842, isl6843, isl6844, isl6845
8 fn9124.11 february 23, 2012 maximum duty cycle isl6840, isl6842, isl6843 94 96 - % isl6841, isl6844, isl6845 47 48 - % minimum duty cycle isl6840, isl6842, isl6843 - - 0 % isl6841, isl6844, isl6845 - - 0 % notes: 9. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. temperature limits established by characterization and are not production tested. 10. this is the v dd current consumed when the device is active but not switching. does not include gate drive current. 11. limits established by characteri zation and are not production tested. 12. adjust v dd above the start threshold and then lower to 15v. electrical specifications recommended operating conditions unless otherwise noted. refer to ?functional block diagram? and ?typical application? schematic on pages 3 and 4. v dd = 15v (note 12), r t = 10k , c t = 3.3nf, t a = -40c to +105c (industrial) or t a = 0c to +70c (commercial) , typical values are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +105c or 0c to +70c . (continued) parameter test conditions min (note 9) typ max (note 9) units typical performance curves figure 1. frequency vs temperature fig ure 2. reference voltage vs temperature figure 3. ea reference vs temperature figure 4. resistance for ct capacitor values given 1.02 1.01 1.00 0.99 0.98 0.97 -40 -10 20 50 80 110 temperature (c) normalized frequency temperature (c) normalized v ref 1.001 1.000 0.999 0.998 0.997 0.996 0.995 -40 -25 -10 5 20 35 50 65 80 95 110 temperature (c) normalized ea reference 1.002 1.000 0.998 0.996 0.994 -40 -25 -10 5 20 35 50 65 80 95 110 10 3 100 10 1 10 20 30 40 50 60 70 80 90 100 rt (k ? ) frequency (khz) 100pf 220pf 330pf 470pf 1.0nf 2.2nf 3.3nf 4.7nf isl6840, isl6841, isl6842, isl6843, isl6844, isl6845
9 fn9124.11 february 23, 2012 pin descriptions rtct - this is the oscillator timing control pin. the operational frequency and maximum duty cycle are set by connecting a resistor, rt, between vref and this pin and a timing capacitor, ct, from this pin to gnd. the oscillator produces a sawtooth waveform with a programmable frequency range up to 2.0mhz. the charge time, t c , the discharge time, t d , the switching frequency, f, and the maximum duty cycle, dmax, can be calculated from equations 1, 2, 3 and 4: figure 4 may be used as a guideline in selecting the capacitor and resistor values required for a given frequency. comp - comp is the output of the error amplifier and the input of the pwm comparator. the control loop frequency compensation network is con nected between the comp and fb pins. fb - the output voltage feedback is connected to the inverting input of the error am plifier through this pin. the non-inverting input of the error amplifier is internally tied to a reference voltage. cs - this is the current sense input to the pwm comparator. the range of the input signal is nominally 0v to 1.0v and has an internal offset of 100mv. gnd - gnd is the power and small signal reference ground for all functions. out - this is the drive output to the power switching device. it is a high current output capable of driving the gate of a power mosfet with peak currents of 1.0a. vdd - v dd is the power connection for the device. the total supply current will depend on the load applied to out. total i dd current is the sum of the operating current and the average output current. knowing the operating frequency, f, and the mosfet gate charge, qg, the average output current can be calculated in equation 5: to optimize noise immunity, bypass v dd to gnd with a ceramic capacitor as close to the vdd and gnd pins as possible. vref - the 5.00v reference voltage output. +1.0/-1.5% tolerance over line, load and operating temperature. bypass to gnd with a 0.1f to 3.3f capaci tor to filter this output as needed. functional description features the isl684x current mode pwms make an ideal choice for low-cost flyback and forward topology applications. with its greatly improved performance ov er industry standard parts, it is the obvious choice for new designs or existing designs which require updating. oscillator the isl684x family of controllers have a sawtooth oscillator with a programmable frequency range to 2mhz, which can be programmed with a resistor from vref and a capacitor to gnd on the rtct pin. (please refer to figure 4 for the resistor and capacitance required for a given frequency.) soft-start operation soft-start must be implemen ted externally. one method, illustrated in figure 5, clamps the voltage on comp. gate drive the isl684x family are capable of sourcing and sinking 1a peak current. to limit the peak current through the ic, an optional external resistor may be placed between the totem-pole output of the ic (out pin) and the gate of the mosfet. this small series resistor also damps any oscillations caused by the resonant tank of the parasitic inductances in the traces of the board and the fet?s input capacitance. slope compensation for applications where the maximum duty cycle is less than 50%, slope compensation may be used to improve noise immunity, particularly at lighter loads. the amount of slope compensation required for noise immunity is determined empirically, but is generally about 10% of the full scale current feedback signal. for applications where the duty cycle is greater than 50%, slope compensation is required to prevent instability. the minimum amount of slope compensation required corresponds to 1/2 the inductor downslope. adding excessive slope compensation, however, results in a control loop that behaves more as a voltage mode controller than as a current mode controller. slope compensation may be added to the cs signal shown in figure 7. t c 0.583 rt ct ? ? (eq. 1) t d rt ? ct 0.0083 rt 4.3 ? ? 0.0083 rt 2.4 ? ? ---------------------------------------------- ?? ?? ln ? ? (eq. 2) f 1t c t d + () ? = (eq. 3) dt c f ? = (eq. 4) (eq. 5) i out qg f = figure 5. soft-start vref comp gnd isl684x isl6840, isl6841, isl6842, isl6843, isl6844, isl6845
10 fn9124.11 february 23, 2012 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fault conditions a fault condition occurs if vref falls below 4.65v. when a fault is detected, out is disabled. when vref exceeds 4.80v, the fault condition clears, and out is enabled. ground plane requirements careful layout is essential for satisfactory operation of the device. a good ground plane must be employed. a unique section of the ground plane must be designated for high di/dt currents associated with the output stage. v dd should be bypassed directly to gnd with good high frequency capacitors. time cs signal (v) downslope current sense signal figure 6. current sense downslope figure 7. slope compensation vref rtct cs isl684x isl6840, isl6841, isl6842, isl6843, isl6844, isl6845
11 fn9124.11 february 23, 2012 isl6840, isl6841, isl6842, isl6843, isl6844, isl6845 package outline drawing m8.15 8 lead narrow body small outline plastic package rev 4, 1/12 detail "a" top view index area 123 -c- seating plane x 45 notes: 1. dimensioning and tolerancing per ansi y14.5m-1994. 2. package length does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 3. package width does not include interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 4. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 5. terminal numbers are shown for reference only. 6. the lead width as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 7. controlling dimension: millimeter. co nverted inch dimensions are not necessarily exact. 8. this outline conforms to jedec publication ms-012-aa issue c. side view ?a side view ?b? 1.27 (0.050) 6.20 (0.244) 5.80 (0.228) 4.00 (0.157) 3.80 (0.150) 0.50 (0.20) 0.25 (0.01) 5.00 (0.197) 4.80 (0.189) 1.75 (0.069) 1.35 (0.053) 0.25(0.010) 0.10(0.004) 0.51(0.020) 0.33(0.013) 8 0 0.25 (0.010) 0.19 (0.008) 1.27 (0.050) 0.40 (0.016) 1.27 (0.050) 5.20(0.205) 1 2 3 4 5 6 7 8 typical recommended land pattern 2.20 (0.087) 0.60 (0.023)
12 fn9124.11 february 23, 2012 isl6840, isl6841, isl6842, isl6843, isl6844, isl6845 package outline drawing m8.118 8 lead mini small outline plastic package rev 4, 7/11 detail "x" side view 2 typical recommended land pattern top view pin# 1 id 0.25 - 0.36 detail "x" 0.10 0.05 (4.40) (3.00) (5.80) h c 1.10 max 0.09 - 0.20 33 gauge plane 0.25 0.95 ref 0.55 0.15 b 0.08 c a-b d 3.00.05 12 8 0.85010 seating plane a 0.65 bsc 3.00.05 4.90.15 (0.40) (1.40) (0.65) d 5 5 side view 1 dimensioning and tolerancing conform to jedec mo-187-aa plastic interlead protrusions of 0.15mm max per side are not dimensions in ( ) are for reference only. dimensions are measured at datum plane "h". plastic or metal protrusions of 0.15mm max per side are not dimensions are in millimeters. 3. 4. 5. 6. notes: 1. 2. and amsey14.5m-1994. included. included. 0.10 c m
13 fn9124.11 february 23, 2012 isl6840, isl6841, isl6842, isl6843, isl6844, isl6845 package outline drawing l8.2x3 8 lead dual flat no-lead plastic package rev 1, 3/10 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.25mm and 0.30mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to asme y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view compies to jedec mo-229 vced-2. 7. (4x) 0.15 index area pin 1 pin #1 c seating plane base plane 0.08 see detail "x" c c 4 6 a b 0.90 0.10 0.05 max 0.05 max 0.20 ref 2.00 3.00 2x 1.50 8x 0.40 0.10 8x 0.25 +0.07/-0.05 index area 6x 0.50 (1.65) (1.50) (8x 0.60) (8x 0.25) (1.80) (2.80) (6x 0.50) 1 8 0.10 a mc b 0.10 c 1.80 +0.10/-0.15 1.65 +0.10/-0.15

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